1. Field of the Invention
The present invention relates to circuits and methods for transmitting and receiving differential signals, and in particular, to circuits and methods for transmitting and receiving low voltage differential signals (LVDS).
2. Related Art
Low voltage differential signaling was developed to allow transmission of electrical signals at very high speeds over inexpensive twisted pair copper cabling. Operating with a differential input termination of 100 ohms, the original target signal speed was approximately 300 megabits per second. However, since its initial introduction, the speed has been pushed significantly higher. As a result, reliable and consistent circuit operation has become increasingly difficult to maintain with the signal speeds now reaching into gigabits per second.
The LVDS signal requirements include a number of specific challenges, including a common mode voltage range of 0.05-2.25 volts, and input signal amplitude of 200-1200 millivolts (differential peak-to-peak), an input voltage range of 0-2.4 volts, and an input current of less than 20 micro-amps.
With increased signal speeds, LVDS circuits have evolved through a number of implementations involving double differential pairs of transistors. Some have included emitter coupled outputs with transconductances tuning across the common mode voltage range or progressive turnoff. Another implementation is as coupled wrap-around style high gain outputs and progressive turnoff. Yet another implementation uses saturation sense turnoff and coupled current-mode resistive load outputs.
Referring to FIG. 1, a more recent circuit architecture uses an all-pass input network that allows for common mode voltage control, a simple N-MOSFET differential pair with simple resistive loads to maximize signal speed. As shown,, the circuitry is biased between the positive VDD and negative VSS power supply terminals. A current source 2 generates a current I which is conducted by transistor N3 and mirrored by transistor N4 to provide the tail current for the differential amplifier transistors N1, N2. The positive INP and negative INN signal phases of the differential input signal VI are applied to respective all-pass networks R1, C1 and R2, C2 across which is coupled a resistive termination of two serially coupled resistances R3, R4. The mid-point of these equal resistances R3, R4 is driven by a common mode, voltage source VCM to establish the common mode voltage VCM at the gate electrodes of the amplifier transistors N1, N2. The resulting differential output signal VOUT is provided at the drain electrodes of the transistors N1, N2.
This type of circuit has a number of advantages, perhaps not the least of which is that it is very simple. Further, implementations have demonstrated operation in excess of 10 gigabits per second while consuming very low power. Additionally, with the all-pass input networks, the input capacitance is less than that of the differential pair transistors N1, N2.
However, there are some disadvantages as well. Such circuitry requires a large input current for fast operation, and the all-pass filter produces signal losses as high as 9 decibels (dB), thereby requiring multiple gain stages to regain such loss. The use of the resistances R1, R2, R3, R4 at the input results in variations in circuit operation due to variations in the respective resistance values. Further, DC common load current is drawn from the input electrodes VINP, VINN, and the AC transfer function of the all-pass networks varies across PVT (manufacturing Processes, Voltage and Temperature). Additionally, it can be difficult to generate the common mode reference voltage VCM, and thermal noise is introduced by the resistances R1, R2, R3, R4.
Moreover, as an LVDS signal receiver, such circuitry must be capable of receiving signals when the common mode voltage can vary over the full power supply range (0-VDD). However, the amplifier transistors N1, N2 can only respond to signals if the common mode voltage is sufficient to turn these transistors N1, N2 on. Hence, while the common mode voltage network VCM, R3, R4 ensures that the transistors N1, N2 will be turned on, such a resistive network produces a significant signal loss, as noted.
Accordingly, it would be desirable to have an improved LVDS circuit architecture that ensures sufficient common mode voltage at the input, but avoids introducing significant signal loss.